As circuit densities increase, the width of shallow trench isolation (STI) trenches decreases while the depth of these trenches remains almost constant. This results in an increased aspect ratio that becomes progressively more difficult to fill without leaving voids.
One method of filling high aspect ration shallow trench isolation (STI) trenches is a chemical vapor deposition (CVD) technique such as high density plasma (HDP) oxide or high aspect ratio (HARP) oxide which employ a deposition/etch/deposition (dep/etch/dep) process. This process involves sequentially depositing material, etching some of it back, and depositing additional material. The etching step reshapes the partially filled trench, opening it at the top so that more material can be deposited before it closes up leaving an interior void.
A primary failure mode for integrated circuits which employ a dep/etch/dep STI fill process is due to STI scratches during the chemical mechanical polish (CMP) planarization process. The scratches are caused by particles formed during the dep/etch/dep STI fill process and also by particles formed when STI geometries break off during the CMP process. The particles formed during deposition or formed when STI geometries break off may get trapped in the CMP pad causing scratches. These scratches may destroy integrated circuit geometries causing yield loss and may also result in deformed integrated circuit patterns during subsequent photolithography steps due to defocus over the particle topography.